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| author | Arnd Bergmann <arnd@arndb.de> | 2025-09-15 15:10:11 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-09-15 15:10:13 +0200 |
| commit | b425afb3488464f38aa433b2d960f3839c7f4187 (patch) | |
| tree | 9768872d495074299cfb72f8964b188d366f2b14 /rust/helpers/build_bug.c | |
| parent | 942d46b4329ca86dc0de254a12024528859867fe (diff) | |
| parent | 7ee0f223cabe9b9384250024fec577c731cbcf72 (diff) | |
Merge tag 'dt64-cleanup-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Minor improvements in ARM64 DTS for v6.18
Add default address cells for interrupt controllers to fix dtc W=1
warnings on Amazon, APM, Socionext and Toshiba boards.
* tag 'dt64-cleanup-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
arm64: dts: toshiba: tmpv7708: Add default GIC address cells
arm64: dts: amazon: alpine-v3: Add default GIC address cells
arm64: dts: amazon: alpine-v2: Add default GIC address cells
arm64: dts: apm: storm: Add default GIC address cells
arm64: dts: socionext: uniphier-pxs3: Add default PCI interrup controller address cells
arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells
Link: https://lore.kernel.org/r/20250909182256.102840-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'rust/helpers/build_bug.c')
0 files changed, 0 insertions, 0 deletions