Merge tag 'thead-clk-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into clk-thead

Pull T-HEAD clock driver updates from Drew Fustini:

 - Describe gate clocks with clk_gate so that clock gates can be clock
   parents. This is similar to the mux clock refactor in 54edba916e29
   ("clk: thead: th1520-ap: Describe mux clocks with clk_mux").
 - Add support for enabling/disabling PLLs. Some PLLs are put into a
   disabled state by the bootloader, and clock driver now has the
   ability to enable them.
 - Set all AXI clocks to CLK_IS_CRITICAL. The AXI crossbar of TH1520 has
   no proper timeout handling, which means gating AXI clocks can easily
   lead to bus timeout and hang the system. All these clock gates are
   ungated by default on system reset.
 - Convert all current CLK_IGNORE_UNUSED usage to CLK_IS_CRITICAL to
   prevent unwanted clock gating.
 - Fix parent of padctrl0 clock, fix parent of DPU pixel clocks and
   support changing DPU pixel clock rate.

* tag 'thead-clk-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux:
  clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL
  clk: thead: support changing DPU pixel clock rate
  clk: thead: add support for enabling/disabling PLLs
  clk: thead: Correct parent for DPU pixel clocks
  clk: thead: th1520-ap: fix parent of padctrl0 clock
  clk: thead: th1520-ap: describe gate clocks with clk_gate

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