diff options
| author | Yazen Ghannam <yazen.ghannam@amd.com> | 2025-09-08 15:40:30 +0000 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2025-09-11 12:22:20 +0200 |
| commit | cfffcf97997bd35f4a59e035523d1762568bdbad (patch) | |
| tree | a5b68a63fbd14476379b572a898a5a5f1cd7471b /scripts/gdb/linux/kasan.py | |
| parent | 9f34032ec0deef58bd0eb7475f1981adfa998648 (diff) | |
x86/mce: Set CR4.MCE last during init
Set the CR4.MCE bit as the last step during init. This brings the MCA
init order closer to what is described in the x86 docs.
x86 docs:
AMD Intel
MCG_CTL
MCA_CONFIG MCG_EXT_CTL
MCi_CTL MCi_CTL
MCG_CTL
CR4.MCE CR4.MCE
Current Linux:
AMD Intel
CR4.MCE CR4.MCE
MCG_CTL MCG_CTL
MCA_CONFIG MCG_EXT_CTL
MCi_CTL MCi_CTL
Updated Linux:
AMD Intel
MCG_CTL MCG_CTL
MCA_CONFIG MCG_EXT_CTL
MCi_CTL MCi_CTL
CR4.MCE CR4.MCE
The new init flow will match Intel's docs, but there will still be a
mismatch for AMD regarding MCG_CTL. However, there is no known issue with this
ordering, so leave it for now.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Nikolay Borisov <nik.borisov@suse.com>
Link: https://lore.kernel.org/20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com
Diffstat (limited to 'scripts/gdb/linux/kasan.py')
0 files changed, 0 insertions, 0 deletions