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| author | Nicolas Frattaroli <nicolas.frattaroli@collabora.com> | 2025-04-29 18:51:55 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-04-29 23:21:49 +0200 |
| commit | 4bf593be2e462623c4c34c7e3b604eb3f8f9de45 (patch) | |
| tree | cf42b9af5cf63fa77f75b0bacd5f489f51a49401 /scripts/gdb/linux/modules.py | |
| parent | 5e6a4ee9799b202fefa8c6264647971f892f0264 (diff) | |
arm64: dts: rockchip: fix Sige5 RTC interrupt pin
Someone made a typo when they added the RTC to the Sige5 DTS, which
resulted in it using interrupts from GPIO0 B0 instead of GPIO0 A0. The
pinctrl entry for it wasn't typoed though, curiously enough.
The Sige5 v1.1 schematic was used to verify that GPIO0 A0 is the correct
pin for the RTC wakeup interrupt, so let's change it to that.
Fixes: 40f742b07ab2 ("arm64: dts: rockchip: Add rk3576-armsom-sige5 board")
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250429-sige5-rtc-oopsie-v1-1-8686767d0f1f@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions