diff options
author | Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> | 2025-08-28 16:46:54 +0530 |
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committer | Borislav Petkov (AMD) <bp@alien8.de> | 2025-09-01 13:05:03 +0200 |
commit | 43b6687ac8777821973d790ff9e9565a84cf6b98 (patch) | |
tree | dbcbda263aa2d9795ee3025f481aa316d48598a4 /scripts/gdb/linux/rbtree.py | |
parent | 8e3714305ad29866d27aa354f09fd03036f44375 (diff) |
x86/apic: Handle EOI writes for Secure AVIC guests
Secure AVIC accelerates the guest's EOI MSR writes for edge-triggered
interrupts.
For level-triggered interrupts, EOI MSR writes trigger a #VC exception with
an SVM_EXIT_AVIC_UNACCELERATED_ACCESS error code. To complete EOI handling,
the #VC exception handler would need to trigger a GHCB protocol MSR write
event to notify the hypervisor about completion of the level-triggered
interrupt. Hypervisor notification is required for cases like emulated
IO-APIC, to complete and clear interrupt in the IO-APIC's interrupt state.
However, #VC exception handling adds extra performance overhead for APIC
register writes. In addition, for Secure AVIC, some unaccelerated APIC
register MSR writes are trapped, whereas others are faulted.
This results in additional complexity in #VC exception handling for
unaccelerated APIC MSR accesses. So, directly do a GHCB protocol based APIC
EOI MSR write from apic->eoi() callback for level-triggered interrupts.
Use WRMSR for edge-triggered interrupts, so that hardware re-evaluates any
pending interrupt which can be delivered to the guest vCPU. For
level-triggered interrupts, re-evaluation happens on return from VMGEXIT
corresponding to the GHCB event for APIC EOI MSR write.
Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tianyu Lan <tiala@microsoft.com>
Link: https://lore.kernel.org/20250828111654.208987-1-Neeraj.Upadhyay@amd.com
Diffstat (limited to 'scripts/gdb/linux/rbtree.py')
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