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| author | Fabrizio Castro <fabrizio.castro.jz@renesas.com> | 2023-06-22 12:33:38 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-07-10 09:31:53 +0200 |
| commit | 63370298426b850220bba40012fb801a48c5fd14 (patch) | |
| tree | e5a3a047aaeaaebbe0425adad844f82916bc6ff5 /scripts/gdb/linux/stackdepot.py | |
| parent | adf6b916c9ee65503d4e7b9650a66e65f5064c3f (diff) | |
clk: renesas: r9a09g011: Add CSI related clocks
The Renesas RZ/V2M SoC comes with 6 CSI IPs (CSI0, CSI1, CSI2
CSI3, CSI4, and CSI5), however Linux is only allowed control
of CSI0 and CSI4.
CSI0 shares its reset and PCLK lines with CSI1, CSI2, and CSI3.
CSI4 shares its reset and PCLK lines with CSI5.
This commit adds support for the relevant clocks.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230622113341.657842-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/stackdepot.py')
0 files changed, 0 insertions, 0 deletions