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| author | Liu Ying <victor.liu@nxp.com> | 2024-11-12 18:05:41 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2024-12-09 17:56:04 +0800 |
| commit | 8446c9585542ee67e2c75d27f9d581360d836bd0 (patch) | |
| tree | 76dc0684c2bc33b71e46666a68d13a33603d073c /scripts/gdb/linux/tasks.py | |
| parent | eead8f3536d5cdb0b300a473ca800249bbcd8329 (diff) | |
arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Set "media_disp2_pix" clock rate to 70MHz
The LVDS panel "multi-inno,mi1010ait-1cp" used on this platform has
a typical pixel clock rate of 70MHz. Set "media_disp2_pix" clock rate
to that rate, instead of the original 68.9MHz. The LVDS serial clock
is controlled by "media_ldb" clock. It should run at 490MHz(7-fold the
pixel clock rate due to single LVDS link). Set "video_pll1" clock rate
and "media_ldb" to 490MHz to achieve that.
This should be able to suppress this LDB driver warning:
[ 17.206644] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (70000000 Hz) does not match requested LVDS clock: 490000000 Hz
This also makes the display mode used by the panel pass mode validation
against pixel clock rate and "media_ldb" clock rate in a certain display
driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions