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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-12-10 19:09:50 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-12-13 11:21:52 +0100 |
| commit | a94253232b0454ae3f45e2a941bbc0a1d5bdb955 (patch) | |
| tree | c7b18760abce7056b2ea299418e17d46d1182105 /scripts/gdb/linux/tasks.py | |
| parent | 880f6c84701cb7735d19f20db89e757086a8fcfa (diff) | |
arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node
Add versa3 clock generator node. It provides the clocks for the Ethernet
PHY, PCIe, audio devices.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20241210170953.2936724-22-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions