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| author | Josua Mayer <josua@solid-run.com> | 2024-11-19 18:33:08 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2025-01-08 09:17:48 +0100 |
| commit | 09cdb973afa7a18ce8e66807daff94609cc4b8a4 (patch) | |
| tree | d49f0f11e61a10281f19975196a6baa6d330a028 /scripts/gdb/linux/utils.py | |
| parent | 40384c840ea1944d7c5a392e8975ed088ecf0b37 (diff) | |
arm64: dts: marvell: cn9131-cf-solidwan: fix cp1 comphy links
Marvell CN913x platforms use common phy framework for configuring and
linking serdes lanes according to their usage.
Each CP (X) features 5 serdes lanes (Y) represented by cpX_comphyY
nodes.
CN9131 SolidWAN uses CP1 serdes lanes 3 and 5 for eth1 and eth2 of CP1
respectively. Devicetree however wrongly links from these ports to the
comphy of CP0.
Replace the wrong links to cp0_comphy with cp1_comphy inside cp1_eth1,
cp1_eth2.
Fixes: 1280840d2030 ("arm64: dts: add description for solidrun cn9131 solidwan board")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions