diff options
| author | Vitaly Rodionov <vitalyr@opensource.cirrus.com> | 2023-05-24 13:52:36 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-05-25 10:54:22 +0100 |
| commit | 13e75f4b03217226f110c5bb5d11720adb5ca9d1 (patch) | |
| tree | e48dc98b332ebbd435d9a26b5edf9341c44a2399 /scripts/gdb/linux/utils.py | |
| parent | f9f46d05003ea6120fa27e01628770a2dac0fa75 (diff) | |
ASoC: cs42l42: Add PLL ratio table values
Add 4.8Mhz 9.6Mhz and 19.2MHz SCLK values
for MCLK 12MHz and 12.288MHz requested by Intel.
Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com>
Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230524125236.57149-1-vitalyr@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions