drm/i915/dsi: Enforce pipeline flush with DSI HS transfer

With all of the boundary conditions when streaming the commands B2B in our
validation (part of the reason we added the flush),  the Flush effectively
serializes the transmission of each command enqueued within the command
dispatcher to one per V. Blank line which simplifies the behavior of the
High Speed Arbitration.

So, unless we absolutely have to burst these to the Sink, we should be
using the Pipeline Flush bit to serialize the commands.

Bspec: 19742, 50193
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14247
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gareth Yu <gareth.yu@intel.com>
Link: https://lore.kernel.org/r/20250509092539.763389-1-gareth.yu@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

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