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| author | Niravkumar L Rabara <niravkumar.l.rabara@intel.com> | 2023-08-01 09:02:31 +0800 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2023-08-08 06:32:34 -0500 |
| commit | 2a29fe831f80f6d9187e49a272d795f3d1b54cdb (patch) | |
| tree | 2c3b6899a495d0d0a9a398c1000e9b85ed502276 /scripts/gdb/linux/utils.py | |
| parent | f23768356be845568545c7baf2c93ca164015cfb (diff) | |
dt-bindings: reset: add reset IDs for Agilex5
Add reset ID definitions required for Intel Agilex5 SoCFPGA, re-use
altr,rst-mgr-s10.h as common header file similar S10 & Agilex.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions