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| author | Matthew Auld <matthew.auld@intel.com> | 2021-07-23 11:50:44 +0100 |
|---|---|---|
| committer | Matthew Auld <matthew.auld@intel.com> | 2021-07-27 09:16:44 +0100 |
| commit | 3821cc7fc0b90a55c3708628336a97993e464dba (patch) | |
| tree | 80c56c7a30f275b0beaa16bef9671031d86cbd49 /scripts/gdb/linux/utils.py | |
| parent | cdb35d1ed6d216978521b75927acb3b8c50a6cac (diff) | |
drm/i915: document caching related bits
Try to document the object caching related bits, like cache_coherent and
cache_dirty.
v2(Ville):
- As pointed out by Ville, fix the completely incorrect assumptions
about the "partial" coherency on shared LLC platforms.
v3(Daniel):
- Fix nonsense about "dirtying" the cache with reads.
v4(Daniel):
- Various improvements, including adding some more details for WT.
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723105045.400841-1-matthew.auld@intel.com
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions