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authorThippeswamy Havalige <thippesw@amd.com>2024-09-22 11:43:17 +0530
committerKrzysztof Wilczyński <kwilczynski@kernel.org>2024-12-18 23:10:31 +0000
commit5c911b4659d55580a15150b7845f13d04c070112 (patch)
tree404c473b75bdd6a4cbecd7a82ad12b2e0ad01aa2 /scripts/gdb/linux/utils.py
parent40384c840ea1944d7c5a392e8975ed088ecf0b37 (diff)
dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5 host1
The Xilinx Versal premium series has CPM5 block which supports two typeA Root Port controller functionality at Gen5 speed. Add compatible string to distinguish between two CPM5 rootport controller1. since Legacy and error interrupt register and bits for both the controllers are at different offsets. Link: https://lore.kernel.org/r/20240922061318.2653503-2-thippesw@amd.com Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
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