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authorMark Brown <broonie@kernel.org>2023-06-10 14:56:26 +0100
committerMark Brown <broonie@kernel.org>2023-06-13 12:11:05 +0100
commit6b7fed83c9455f64a1509a9e1d512a92edaaf44e (patch)
tree0d1d594f94587f52189440178e27091d39db52fa /scripts/gdb/linux/utils.py
parentbb1bd25ad79cf21b8fa4c0eae474307b2d24b268 (diff)
ASoC: cs42l42: Use maple tree register cache
The cs42l42 can only support single register read and write operations so does not benefit from block writes. This means it gets no benefit from using the rbtree register cache over the maple tree register cache so convert it to use maple trees instead, it is more modern. Acked-by: David Rhodes <david.rhodes@cirrus.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-6-b806c4cbd1d4@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
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