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author | Evan Green <evan@rivosinc.com> | 2023-05-09 11:25:02 -0700 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-19 09:51:22 -0700 |
commit | 82e9c66e81c814e20ee2a3aafb60a9012c79fb40 (patch) | |
tree | 2f4aeeb8cd3205f32f6f521ba38fbe97872b991b /scripts/gdb/linux/utils.py | |
parent | c6699baf10647b87b075bf6c65d25b4cd52d4830 (diff) |
RISC-V: Track ISA extensions per hart
The kernel maintains a mask of ISA extensions ANDed together across all
harts. Let's also keep a bitmap of ISA extensions for each CPU. Although
the kernel is currently unlikely to enable a feature that exists only on
some CPUs, we want the ability to report asymmetric CPU extensions
accurately to usermode.
Note that riscv_fill_hwcaps() runs before the per_cpu_offsets are built,
which is why I've used a [NR_CPUS] array rather than per_cpu() data.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230509182504.2997252-3-evan@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions