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| author | Hal Feng <hal.feng@starfivetech.com> | 2023-04-01 19:19:30 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-04-05 15:50:11 +0100 |
| commit | 8868caa2a073cdac8a3c28e4e30cf72fe6b44f22 (patch) | |
| tree | f15321ef48adfba80be82ad97a5670547bc0624a /scripts/gdb/linux/utils.py | |
| parent | 8406d19ca0493aa8b4b83314efe57219c8bb92b6 (diff) | |
dt-bindings: riscv: Add SiFive S7 compatible
Add a new compatible string in cpu.yaml for SiFive S7 CPU
core which is used on SiFive U74-MC core complex etc.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions