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| author | Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2025-05-23 11:50:40 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2025-05-26 13:18:16 +0530 |
| commit | 88d7e284b24ee3e16b97630536c6aa06e58941db (patch) | |
| tree | d19918072d3c350caa9d50168753ce6e1effbd84 /scripts/gdb/linux/utils.py | |
| parent | d94a92b7d0a4424936b6a5aa25038a769cdd4ba8 (diff) | |
drm/i915/color: Do not pre-load LUTs with DB registers
Since Double Buffered LUT registers can be written in active region
no need to preload them.
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://lore.kernel.org/r/20250523062041.166468-11-chaitanya.kumar.borah@intel.com
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions