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| author | Stephen Boyd <sboyd@kernel.org> | 2023-06-08 17:40:12 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-06-08 17:40:12 -0700 |
| commit | f73b836edfef23054c227712bbdb9d4c23e00440 (patch) | |
| tree | 2695947f63ccc22f623fd8c13eaf4ec234f7b3a2 /scripts/gdb/linux/utils.py | |
| parent | ac9a78681b921877518763ba0e89202254349d1b (diff) | |
| parent | d1c20885d3b01e6a62e920af4b227abd294d22f3 (diff) | |
Merge tag 'renesas-clk-for-v6.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add PWM clock on Renesas R-Car V3U
- Fix PLL5 on Renesas RZ/G2L and RZ/V2L
* tag 'renesas-clk-for-v6.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
clk: renesas: r8a779a0: Add PWM clock
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions