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author | Ben Skeggs <bskeggs@redhat.com> | 2022-06-01 20:47:38 +1000 |
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committer | Ben Skeggs <bskeggs@redhat.com> | 2022-11-09 10:44:50 +1000 |
commit | 06db7fded6dec88772a65c5a39af12ba4dc2ad38 (patch) | |
tree | d00ff73679dd75931c7625880903e1b301184600 /scripts/generate_rust_analyzer.py | |
parent | 7ac293328122075a2afc40a4089e7afc6cbc26eb (diff) |
drm/nouveau/fifo: add new channel classes
Exposes a bunch of the new features that became possible as a result
of the earlier commits. DRM will build on this in the future to add
support for features such as SCG ("async compute") and multi-device
rendering, as part of the work necessary to be able to write a half-
decent vulkan driver - finally.
For the moment, this just crudely ports DRM to the API changes.
- channel class interfaces now the same for all HW classes
- channel group class exposed (SCG)
- channel runqueue selector exposed (SCG)
- channel sub-device id control exposed (multi-device rendering)
- channel names in logging will reflect creating process, not fd owner
- explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer
- drm is smarter about determining the appropriate channel class to use
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions