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author | Clément Léger <cleger@rivosinc.com> | 2025-05-23 12:19:25 +0200 |
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committer | Palmer Dabbelt <palmer@dabbelt.com> | 2025-06-04 15:11:05 -0700 |
commit | 1317045a7d6f397904d105f6d40dc9787876a34b (patch) | |
tree | 6bdde0ab2bfe2007e9c958d7698e714d72c56e23 /scripts/generate_rust_analyzer.py | |
parent | 9f9f6fdd1dc6791bcfe251160a96a446199f85ce (diff) |
riscv: misaligned: declare misaligned_access_speed under CONFIG_RISCV_MISALIGNED
While misaligned_access_speed was defined in a file compile with
CONFIG_RISCV_MISALIGNED, its definition was under
CONFIG_RISCV_SCALAR_MISALIGNED. This resulted in compilation problems
when using it in a file compiled with CONFIG_RISCV_MISALIGNED.
Move the declaration under CONFIG_RISCV_MISALIGNED so that it can be
used unconditionnally when compiled with that config and remove the check
for that variable in traps_misaligned.c.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20250523101932.1594077-9-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions