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author | Palmer Dabbelt <palmer@rivosinc.com> | 2025-05-08 10:01:02 -0700 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2025-05-08 10:08:01 -0700 |
commit | 259aaf03d7a03fe3c2f909deaeea7ce84ed47880 (patch) | |
tree | ff9300fe348eaa6f72623196652a02ca0f69aa80 /scripts/generate_rust_analyzer.py | |
parent | 85f79dece58373e29ece0507fda378cdc0e617cc (diff) | |
parent | f6bff7827a48e59cff1ef98aae72452d65174e0c (diff) |
Merge patch series "riscv: uaccess: optimisations"
Cyril Bur <cyrilbur@tenstorrent.com> says:
This series tries to optimize riscv uaccess by allowing the use of
user_access_begin() and user_access_end() which permits grouping user accesses
and avoiding the CSR write penalty for each access.
The error path can also be optimised using asm goto which patches 3 and 4
achieve. This will speed up jumping to labels by avoiding the need of an
intermediary error type variable within the uaccess macros
I did read the discussion this series generated. It isn't clear to me
which direction to take the patches, if any.
* b4-shazam-merge:
riscv: uaccess: use 'asm_goto_output' for get_user()
riscv: uaccess: use 'asm goto' for put_user()
riscv: uaccess: use input constraints for ptr of __put_user()
riscv: implement user_access_begin() and families
riscv: save the SR_SUM status over switches
Link: https://lore.kernel.org/r/20250410070526.3160847-1-cyrilbur@tenstorrent.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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