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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-06-17 20:07:51 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-06-23 17:50:00 +0300 |
| commit | 42a7bf8aa730606ae89b60c1058c50866f240e5d (patch) | |
| tree | 635de913a50a32079437bf17750fdb5a5151c3b0 /scripts/generate_rust_analyzer.py | |
| parent | 266907bb491f2bdd731139792b5a5056b6d0a482 (diff) | |
drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL
Supposedly nothing post-MTL (even BMG) needs the pipe DMC clock
gating w/a (Wa_16015201720), so don't apply it.
TODO: check if the ADL/DG2 "clock gating needed during DMC loading" part
is actually needed, not seeing anything in the docs about it...
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-2-ville.syrjala@linux.intel.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions