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authorAo Zhong <hacc1225@gmail.com>2022-10-25 23:17:49 +0200
committerAlex Deucher <alexander.deucher@amd.com>2022-10-27 15:12:08 -0400
commit58ddbecb14c792b7fe0d92ae5e25c9179d62ff25 (patch)
treea5888a5ff80cf11a1da5073f063a4cadf0524fcd /scripts/generate_rust_analyzer.py
parent64a9f19a5addffe585e872945c0544fed24f83a8 (diff)
drm/amd/display: move remaining FPU code to dml folder
pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; these two operations in dcn32/dcn32_resource.c still need to use FPU, This will cause compilation to fail on ARM64 platforms because -mgeneral-regs-only is enabled by default to disable the hardware FPU. Therefore, imitate the dcn31_zero_pipe_dcc_fraction function in dml/dcn31/dcn31_fpu.c, declare the dcn32_zero_pipe_dcc_fraction function in dcn32_fpu.c, and move above two operations into this function. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Ao Zhong <hacc1225@gmail.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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