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| author | Vignesh Raghavendra <vigneshr@ti.com> | 2023-03-20 10:19:34 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2023-03-20 12:34:25 -0500 |
| commit | 6974371cab1c488a53960945cb139b20ebb5f16b (patch) | |
| tree | dd45411797f90c3f9f9674b25ef9095f1b4e17a4 /scripts/generate_rust_analyzer.py | |
| parent | 436b288687176bf4d2c1cd25b86173e5a1649a60 (diff) | |
arm64: dts: ti: k3-am625: Correct L2 cache size to 512KB
Per AM62x SoC datasheet[0] L2 cache is 512KB.
[0] https://www.ti.com/lit/gpn/am625 Page 1.
Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230320044935.2512288-1-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions