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authorVille Syrjälä <ville.syrjala@linux.intel.com>2025-06-17 20:07:55 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2025-06-23 17:50:07 +0300
commit761748679e80cc429f035bcb64662becf0ecf4f6 (patch)
tree9563308b018b53197a48f47f5d55ecf7add4fc84 /scripts/generate_rust_analyzer.py
parentc541ad77a394e186a34e6af5e1b6057827c42659 (diff)
drm/i915/dmc: Reload pipe DMC state on TGL when enabling pipe A
On TGL/derivatives the entire pipe DMC state (program + MMIO) is lost when PG1 is disabled, and the main DMC does not restore any of it. Reload the state when enabling a pipe. The other option would be to not load the pipe DMC at all since it's only needed for "fast LACE" (which we don't use) on these platforms. But let's keep it around just in case we ever decide that "fast LACE" is something we want. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-6-ville.syrjala@linux.intel.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
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