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authorHeiko Carstens <hca@linux.ibm.com>2025-05-19 18:07:11 +0200
committerHeiko Carstens <hca@linux.ibm.com>2025-05-21 12:02:27 +0200
commitc4abe6234246c75cdc43326415d9cff88b7cf06c (patch)
tree2d5ab76238bb041a052dddee1ceac78c1fae3bd6 /scripts/generate_rust_analyzer.py
parentd35ef47a43f8a01252e89b1fd4a52c91017b5d59 (diff)
s390/pci: Fix __pcilg_mio_inuser() inline assembly
Use "a" constraint for the shift operand of the __pcilg_mio_inuser() inline assembly. The used "d" constraint allows the compiler to use any general purpose register for the shift operand, including register zero. If register zero is used this my result in incorrect code generation: 8f6: a7 0a ff f8 ahi %r0,-8 8fa: eb 32 00 00 00 0c srlg %r3,%r2,0 <---- If register zero is selected to contain the shift value, the srlg instruction ignores the contents of the register and always shifts zero bits. Therefore use the "a" constraint which does not permit to select register zero. Fixes: f058599e22d5 ("s390/pci: Fix s390_mmio_read/write with MIO") Cc: stable@vger.kernel.org Reported-by: Niklas Schnelle <schnelle@linux.ibm.com> Reviewed-by: Niklas Schnelle <schnelle@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
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