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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-05-08 20:17:14 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-05-08 20:17:14 +0200 |
| commit | d4da08ea37d2c84aedcf1ce9554938aabfb0714f (patch) | |
| tree | 696e848084ccb67d1867969637ec7f66483e57d5 /scripts/generate_rust_analyzer.py | |
| parent | aff664cc8cbc5c28e5aa57dc4201c34497f3c871 (diff) | |
| parent | f21923f3f410f84528b5e7bdcbe4afdc6f07010c (diff) | |
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag3' into renesas-clk-for-v6.16
Renesas RZ/G3E XSPI and GBETH Core DT Binding Definitions
XSPI and Gigabit Ethernet PTP reference core clock DT binding
definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and
DT source files.
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions