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author | Linus Torvalds <torvalds@linux-foundation.org> | 2025-05-21 17:24:18 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2025-05-21 17:24:18 -0700 |
commit | d608703fcdd9e9538f6c7a0fcf98bf79b1375b60 (patch) | |
tree | 4310b9d55a31042cc0aba309047acf9cc984c23b /scripts/generate_rust_analyzer.py | |
parent | 4a95bc121ccdaee04c4d72f84dbfa6b880a514b6 (diff) | |
parent | 6a56880562d470b7bbdd1d955ff3fad4ad73a74f (diff) |
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"Fixes for some SoC clk drivers:
- Define the gate clk for the OTG PHY on Rockchip RK3576 so the nvmem
driver actually works
- Initialize clk_hw_onecell_data::num before accessing the 'hws'
array to keep UBSAN happy
- Fix a perf degradation on the Allwinner D1 MMC clk that was making
things half bad
- Fix the Allwinner SNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT macro to have
proper order of arguments"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: sunxi-ng: d1: Add missing divider for MMC mod clocks
clk: s2mps11: initialise clk_hw_onecell_data::num before accessing ::hws[] in probe()
clk: sunxi-ng: fix order of arguments in clock macro
clk: rockchip: rk3576: define clk_otp_phy_g
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions