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| author | Sean Anderson <sean.anderson@linux.dev> | 2025-02-06 15:10:35 -0500 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2025-02-10 18:53:40 -0800 |
| commit | eb80520e8a5be676cd546c2503aa78653ff4b026 (patch) | |
| tree | 34077209dd83a31f46ca581b797710dd57753f23 /scripts/generate_rust_analyzer.py | |
| parent | d048c717df33baf337a58b5d74c855a74abf4e04 (diff) | |
net: xilinx: axienet: Get coalesce parameters from driver state
The cr variables now contain the same values as the control registers
themselves. Extract/calculate the values from the variables instead of
saving the user-specified values. This allows us to remove some
bookeeping, and also lets the user know what the actual coalesce
settings are.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed by: Shannon Nelson <shannon.nelson@amd.com>
Link: https://patch.msgid.link/20250206201036.1516800-4-sean.anderson@linux.dev
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions