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| author | MD Danish Anwar <danishanwar@ti.com> | 2024-11-13 16:39:54 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2024-12-26 14:00:54 -0600 |
| commit | f7ed5ae30cf395d92a3e1e3c843fa86ce96167b8 (patch) | |
| tree | 348f1eadef0a5093f7b60a04a9feff3aad89e46c /scripts/generate_rust_analyzer.py | |
| parent | 0a41157c5a988520debb656325722f401163eca3 (diff) | |
dt-bindings: soc: ti: pruss: Add clocks for ICSSG
The ICSSG module has 7 clocks for each instance.
These clocks are ICSSG0_CORE_CLK, ICSSG0_IEP_CLK, ICSSG0_ICLK,
ICSSG0_UART_CLK, RGMII_MHZ_250_CLK, RGMII_MHZ_50_CLK and RGMII_MHZ_5_CLK
These clocks are described in AM64x TRM Section 6.4.3 Table 6-398.
Add these clocks to the dt binding of ICSSG.
Link: https://www.ti.com/lit/pdf/spruim2 (AM64x TRM)
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241113110955.3876045-2-danishanwar@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions