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authorJohn Harrison <John.C.Harrison@Intel.com>2025-04-17 14:33:03 -0700
committerJohn Harrison <John.C.Harrison@Intel.com>2025-04-22 10:24:47 -0700
commitfa597710be6e6625b875d95c717f66b7ab83b986 (patch)
tree89a4fbe12605a7b011a180ae4f47946ee5785e05 /scripts/generate_rust_analyzer.py
parent8393f3e155d902bd66c3033b073ec10d1409b2ee (diff)
drm/xe/guc: Cache DSS info when creating capture register list
Calculating the DSS id (index of a steered register) currently requires reading state from the hwconfig table and that currently requires dynamically allocating memory. The GuC based register capture (for dev core dumps) includes this index as part of the register name in the dump. However, it was calculating said index at the time of the dump for every dump. That is wasteful. It also breaks anyone trying to do the dump at a time when memory allocations are not allowed. So rather than calculating on every print, just calculate at start of day when creating the register list in the first place. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20250417213303.3021243-1-John.C.Harrison@Intel.com
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