Merge tag 'riscv-mw1-6.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next

riscv patches for 6.15-rc1

* A bunch of fixes:
  - We were missing a secondary mmu notifier call when flushing the tlb which is required for IOMMU
  - Fix ftrace panics by saving the registers as expected by ftrace
  - Fix a couple of stimecmp usage related to cpu hotplug
  - Fix a bunch of issues in the misaligned probing handling

* Perf improvements:
  - Introduce support for runtime constant improving perf of d_hash()
  - Add support for huge pfnmaps to improve tlb utilization
  - Use Zawrs to improve smp_cond_load8/16() used by the queued spinlocks

* Hwprobe additions:
  - Add support for Zicntr and Zihpm
  - Add support for Zaamo and Zalrsc
  - Add support for bfloat16 extensiosn
  - Add support for Zicbom (only enabling clean and flush, not inval for security reasons)

* Misc:
  - Add a kernel parameter to bypass the misaligned speed probing since we can't rely on Zicclsm

* tag 'riscv-mw1-6.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux: (1585 commits)
  riscv: Add runtime constant support
  riscv: Move nop definition to insn-def.h
  Documentation/kernel-parameters: Add riscv unaligned speed parameters
  riscv: Add parameter for skipping access speed tests
  riscv: Fix set up of vector cpu hotplug callback
  riscv: Fix set up of cpu hotplug callbacks
  riscv: Change check_unaligned_access_speed_all_cpus to void
  riscv: Fix check_unaligned_access_all_cpus
  riscv: Fix riscv_online_cpu_vec
  riscv: Annotate unaligned access init functions
  KVM: riscv: selftests: Add Zaamo/Zalrsc extensions to get-reg-list test
  RISC-V: KVM: Allow Zaamo/Zalrsc extensions for Guest/VM
  riscv: hwprobe: export Zaamo and Zalrsc extensions
  riscv: add parsing for Zaamo and Zalrsc extensions
  dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description
  riscv: fgraph: Fix stack layout to match __arch_ftrace_regs argument of ftrace_return_to_handler
  riscv: fgraph: Select HAVE_FUNCTION_GRAPH_TRACER depends on HAVE_DYNAMIC_FTRACE_WITH_ARGS
  riscv: Fix missing __free_pages() in check_vector_unaligned_access()
  riscv: Fix the __riscv_copy_vec_words_unaligned implementation
  riscv: mm: Don't use %pK through printk
  ...

1 files changed, 18 insertions, 0 deletions

diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs
index 0d00ac3723b5..4fd6b6ab3e32 100644
--- a/scripts/generate_rust_target.rs
+++ b/scripts/generate_rust_target.rs
@@ -165,6 +165,18 @@ impl KernelConfig {
         let option = "CONFIG_".to_owned() + option;
         self.0.contains_key(&option)
     }
+
+    /// Is the rustc version at least `major.minor.patch`?
+    fn rustc_version_atleast(&self, major: u32, minor: u32, patch: u32) -> bool {
+        let check_version = 100000 * major + 100 * minor + patch;
+        let actual_version = self
+            .0
+            .get("CONFIG_RUSTC_VERSION")
+            .unwrap()
+            .parse::<u32>()
+            .unwrap();
+        check_version <= actual_version
+    }
 }
 
 fn main() {
@@ -182,6 +194,9 @@ fn main() {
         }
     } else if cfg.has("X86_64") {
         ts.push("arch", "x86_64");
+        if cfg.rustc_version_atleast(1, 86, 0) {
+            ts.push("rustc-abi", "x86-softfloat");
+        }
         ts.push(
             "data-layout",
             "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128",
@@ -215,6 +230,9 @@ fn main() {
             panic!("32-bit x86 only works under UML");
         }
         ts.push("arch", "x86");
+        if cfg.rustc_version_atleast(1, 86, 0) {
+            ts.push("rustc-abi", "x86-softfloat");
+        }
         ts.push(
             "data-layout",
             "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:32-n8:16:32-S128",