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authorRobert Richter <rrichter@amd.com>2025-05-09 17:06:59 +0200
committerDave Jiang <dave.jiang@intel.com>2025-05-09 09:57:43 -0700
commit98a863fee2406f92cf172659b2390212e72a3313 (patch)
treef4296e07fafe1935e610f5d57349b99327ecbf3a /scripts/lib/kdoc/kdoc_files.py
parentd90acdf49e18029cfe4194475c45ef143657737a (diff)
cxl: Add a dev_dbg() when a decoder was added to a port
Improve debugging by adding and unifying messages whenever a decoder was added to a port. It is especially useful to get the decoder mapping of the involved CXL host bridge or PCI device. This avoids a complex lookup of the decoder/port/device mappings in sysfs. Example log messages: cxl_acpi ACPI0017:00: decoder0.0 added to root0 cxl_acpi ACPI0017:00: decoder0.1 added to root0 ... pci0000:e0: decoder1.0 added to port1 pci0000:e0: decoder1.1 added to port1 ... cxl_mem mem0: decoder5.0 added to endpoint5 cxl_mem mem0: decoder5.1 added to endpoint5 Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-15-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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