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| author | Alexander Shiyan <eagle.alexander923@gmail.com> | 2025-04-08 09:46:12 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-04-10 14:28:14 +0200 |
| commit | 831a8ac72264426ccd0ee5d2b0d74491ea7d2bfb (patch) | |
| tree | 1567f6922908da0a9d57fb734d558c94ba58d569 /scripts/lib/kdoc/kdoc_output.py | |
| parent | 0af2f6be1b4281385b618cb86ad946eded089ac8 (diff) | |
clk: rockchip: rk3588: Add PLL rate for 1500 MHz
At least one RK3588 clock (CPLL) uses 1.5 GHz, so let's add
that frequency to the PLL table.
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Link: https://lore.kernel.org/r/20250408064612.41359-1-eagle.alexander923@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'scripts/lib/kdoc/kdoc_output.py')
0 files changed, 0 insertions, 0 deletions