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authorConor Dooley <conor.dooley@microchip.com>2025-05-12 14:48:14 +0100
committerConor Dooley <conor.dooley@microchip.com>2025-05-12 16:53:29 +0100
commitd58a73c96d8ae87936579689af1dd60a09bda432 (patch)
tree1f847191c7edb43dae93baa5f72df246a365563f /scripts/lib/kdoc/kdoc_output.py
parent82e8c6931074e1fa1bdbdcc01604e164c42f989e (diff)
dt-bindings: cache: add specific RZ/Five compatible to ax45mp
When the binding was originally written, it was assumed that all ax45mp-caches had the same properties etc. This has turned out to be incorrect, as the QiLai SoC has a different number of cache-sets. Add a specific compatible for the RZ/Five for property enforcement and in case there turns out to be additional differences between these implementations of the cache controller. Acked-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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