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authorNicolas Frattaroli <nicolas.frattaroli@collabora.com>2025-05-02 13:03:09 +0200
committerHeiko Stuebner <heiko@sntech.de>2025-05-05 22:39:24 +0200
commite277168cabe9fd99e647f5dad0bc846d5d6b0093 (patch)
treeb8b0194e9a4c0f067b11b20d7fb3d4b4b2426034 /scripts/lib/kdoc/kdoc_output.py
parent70a114daf2077472e58b3cac23ba8998e35352f4 (diff)
clk: rockchip: introduce GRF gates
Some rockchip SoCs, namely the RK3576, have bits in a General Register File (GRF) that act just like clock gates. The downstream vendor kernel simply maps over the already mapped GRF range with a generic clock gate driver. This solution isn't suitable for upstream, as a memory range will be in use by multiple drivers at the same time, and it leaks implementation details into the device tree. Instead, implement this with a new clock branch type in the Rockchip clock driver: GRF gates. Somewhat akin to MUXGRF, this clock branch depends on the type of GRF, but functions like a gate instead. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-3-376cef19dd7c@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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