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| author | Arnd Bergmann <arnd@arndb.de> | 2025-05-21 23:57:48 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-05-21 23:57:49 +0200 |
| commit | 00000994fe32264d45e4e011d258779bfb26f6b0 (patch) | |
| tree | 128959c71222d8e5c8f862057717bfcea2b6eaa4 /scripts/lib/kdoc/kdoc_parser.py | |
| parent | ced334a21c58dd7e35f39ea2992419cbd92b1849 (diff) | |
| parent | d50108706a63dfd896db42172bf9f6aebec219c5 (diff) | |
Merge tag 'riscv-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.16
Starfive:
All Starfive this time (again), enabling the usb3 port on the framework
laptop mainboard, and a few cleanup patches that are syncing things with
the dts used by U-Boot.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader
riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
riscv: dts: starfive: jh7110-common: use macros for MMC0 pins
riscv: dts: starfive: fml13v01: enable USB 3.0 port
Link: https://lore.kernel.org/r/20250516-gap-exploring-f8f516ab4e1c@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'scripts/lib/kdoc/kdoc_parser.py')
0 files changed, 0 insertions, 0 deletions