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| author | Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> | 2025-03-28 15:58:32 +0530 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2025-04-19 19:42:43 +0530 |
| commit | 178af54a678d08735233e070a9329651e1589587 (patch) | |
| tree | e17dac36e8b9f409e72f52fb7182f32ac6fe12c2 /scripts/lib/kdoc/kdoc_parser.py | |
| parent | f9eb654fb194e7c404d4984481a18edb9b1c1d7c (diff) | |
PCI: Add lane equalization register offsets
As per PCIe spec 6.0.1, add PCIe lane equalization register offset for
data rates 8.0 GT/s, 32.0 GT/s and 64.0 GT/s.
Also add a macro for defining data rate 64.0 GT/s physical layer capability
ID.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://patch.msgid.link/20250328-preset_v6-v9-4-22cfa0490518@oss.qualcomm.com
Diffstat (limited to 'scripts/lib/kdoc/kdoc_parser.py')
0 files changed, 0 insertions, 0 deletions