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authorJason Gunthorpe <jgg@nvidia.com>2024-12-05 11:40:15 -0400
committerWill Deacon <will@kernel.org>2024-12-09 22:41:42 +0000
commit9b640ae7fbba13d45a8b9712dff2911a0c2b5ff4 (patch)
treed66e69b5e3cb83df55fd0f1f87b76a6356bea8eb /scripts/lib/kdoc/kdoc_parser.py
parentd814b70b9b901c823ddedd12757ca4a19b18c8f7 (diff)
iommu/arm-smmuv3: Update comments about ATS and bypass
The SMMUv3 spec has a note that BYPASS and ATS don't work together under the STE EATS field definition. However there is another section "13.6.4 Full ATS skipping stage 1" that explains under certain conditions BYPASS and ATS do work together if the STE is using S1DSS to select BYPASS and the CD table has the possibility for a substream. When these comments were written the understanding was that all forms of BYPASS just didn't work and this was to be a future problem to solve. It turns out that ATS and IDENTITY will always work just fine: - If STE.Config = BYPASS then the PCI ATS is disabled - If a PASID domain is attached then S1DSS = BYPASS and ATS will be enabled. This meets the requirements of 13.6.4 to automatically generate 1:1 ATS replies on the RID. Update the comments to reflect this. Fixes: 7497f4211f4f ("iommu/arm-smmu-v3: Make changing domains be hitless for ATS") Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/0-v1-f27174f44f39+27a33-smmuv3_ats_note_jgg@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
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