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| author | Timur Kristóf <timur.kristof@gmail.com> | 2025-07-31 11:43:47 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-08-18 17:03:16 -0400 |
| commit | 1ae45b5d4f371af8ae51a3827d0ec9fe27eeb867 (patch) | |
| tree | 3ee3a1badddf5455ba17674d97b7f4dfebdea991 /scripts/lib/kdoc/kdoc_re.py | |
| parent | 427980c1cbd22bb256b9385f5ce73c0937562408 (diff) | |
drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%
Adjust the nominal (and performance) clocks for DCE 8-10,
and set them to 625 MHz, which is the value used by the legacy
display code in amdgpu_atombios_get_clock_info.
This was tested with Hawaii, Tonga and Fiji.
These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz.
The extra 15% clock was added as a workaround for a Polaris issue
which uses DCE 11, and should not have been used on DCE 8-10 which
are already hardcoded to the highest possible display clock.
Unfortunately, the extra 15% was mistakenly copied and kept
even on code paths which don't affect Polaris.
This commit fixes that and also adds a check to make sure
not to exceed the maximum DCE 8-10 display clock.
Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/lib/kdoc/kdoc_re.py')
0 files changed, 0 insertions, 0 deletions
