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authorLorenzo Pieralisi <lpieralisi@kernel.org>2025-07-03 12:25:09 +0200
committerMarc Zyngier <maz@kernel.org>2025-07-08 18:35:51 +0100
commite62e1e9493aa7aeba6670db6373031533a4d4ced (patch)
treefb35c4c637a34766e8e9ed70546b5fc02be4dfa5 /scripts/patch-kernel
parentba1004f861d16f24179f14f13f70c09227ccbffb (diff)
arm64: Add support for GICv5 GSB barriers
The GICv5 architecture introduces two barriers instructions (GSB SYS, GSB ACK) that are used to manage interrupt effects. Rework macro used to emit the SB barrier instruction and implement the GSB barriers on top of it. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-19-12e71f1b3528@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
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