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author | Michal Wilczynski <michal.wilczynski@intel.com> | 2023-07-10 17:03:33 +0300 |
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committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2023-07-14 17:59:40 +0200 |
commit | 4f37ab5e05df9a30d64663266c7f4ba3a1407c68 (patch) | |
tree | a343c9ee965e064460e273d0fbee72e94f748f0b /scripts/rustdoc_test_builder.rs | |
parent | c9e6c5e64f0c00612dc429bc401da0ea673e5130 (diff) |
ACPI: processor: Clear C_C2C3_FFH and C_C1_FFH in arch_acpi_set_proc_cap_bits()
Currently arch_acpi_set_proc_cap_bits() clears ACPI_PDC_C_C2C3_FFH bit in
case MWAIT instruction is not supported.
It should also clear ACPI_PDC_C_C1_FFH, as when MWAIT is not supported,
C1 is entered by executing the HLT instruction.
Quote from the C_C1_FFH description:
"If set, OSPM is capable of performing native C State instructions (beyond
halt) for the C1 handler in multi-processor configurations". As without
MWAIT there is no native C-state instructions beyond HALT, this bit
should be toggled off."
Clear ACPI_PDC_C_C1_FFH and ACPI_PDC_C_C2C3_FFH in
arch_acpi_set_proc_cap_bits() in case MWAIT is not supported or
overridden.
Remove setting those bits from the processor_pdc.c code.
Suggested-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Michal Wilczynski <michal.wilczynski@intel.com>
[ rjw: Subject and changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'scripts/rustdoc_test_builder.rs')
0 files changed, 0 insertions, 0 deletions