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authorPritesh Patel <pritesh.patel@einfochips.com>2025-03-20 16:24:44 +0530
committerConor Dooley <conor.dooley@microchip.com>2025-04-07 16:53:46 +0100
commit2eb68366159a94cdf61b97fbc9ab230bef94313f (patch)
treee5b1d52e8340a85d5a77ab94fa6c04722f7c6aeb /scripts
parent0af2f6be1b4281385b618cb86ad946eded089ac8 (diff)
dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility
This cache controller is also used on the ESWIN EIC7700 SoC. However, it have 256KB private L2 Cache and shared L3 Cache of 4MB. So add dedicated compatible string for it. Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts')
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