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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2025-11-19 16:35:18 +0200 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2025-11-25 11:17:17 +0530 |
| commit | e7534e790557e9ee18a2c497dc89a6b31e435e48 (patch) | |
| tree | a2706410b47612d06cc49adf442ef8e6fc2402a6 /tools/docs/check-variable-fonts.py | |
| parent | 3a8660878839faadb4f1a6dd72c3179c1df56787 (diff) | |
dt-bindings: PCI: Add Renesas RZ/G3S PCIe controller binding
The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express
Base Specification 4.0. It is designed for root complex applications and
features a single-lane (x1) implementation. Add binding documentation for
it.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251119143523.977085-2-claudiu.beznea.uj@bp.renesas.com
Diffstat (limited to 'tools/docs/check-variable-fonts.py')
0 files changed, 0 insertions, 0 deletions