diff options
| author | Uma Shankar <uma.shankar@intel.com> | 2025-12-03 14:22:07 +0530 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2025-12-04 19:43:47 +0200 |
| commit | 82caa1c8813fb333303f21dd553c85d36ffb01fe (patch) | |
| tree | eef4d2a4b54c7e7984c2957f0cff5fbfab0d4f17 /tools/lib/python/feat/parse_features.py | |
| parent | 3b7476e786c2250177c5db0b6b9f1348813b9ce0 (diff) | |
drm/i915/color: Program Pre-CSC registers
Add callback to program Pre-CSC LUT for TGL and beyond
v2: Add DSB support
v3: Add support for single segment 1D LUT color op
v4:
- s/drm_color_lut_32/drm_color_lut32/ (Simon)
- Change commit message (Suraj)
- Improve comments (Suraj)
- Remove multisegmented programming, to be added later
- Remove dead code for SDR planes, add when needed
BSpec: 50411, 50412, 50413, 50414
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://patch.msgid.link/20251203085211.3663374-12-uma.shankar@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/lib/python/feat/parse_features.py')
0 files changed, 0 insertions, 0 deletions