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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-10-23 22:07:24 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-10-27 12:15:00 +0100 |
| commit | 07525a693a5ff6592668a0fd647153e4b4933cae (patch) | |
| tree | e299a289e46c4812db0a3542b946def71acc855a /tools/lib/python/kdoc/parse_data_structs.py | |
| parent | 861df8792c69d903fbb705a0d314bfdd5546d72b (diff) | |
clk: renesas: r9a09g056: Add clock and reset entries for ISP
Add entries detailing the clocks and resets for the ISP in the
RZ/V2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023210724.666476-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/lib/python/kdoc/parse_data_structs.py')
0 files changed, 0 insertions, 0 deletions