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| author | Ovidiu Panait <ovidiu.panait.rb@renesas.com> | 2025-10-20 14:31:05 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-10-23 16:31:01 +0200 |
| commit | 919bf298dc9fe2cee5abfacb281fb201cda65a44 (patch) | |
| tree | 58c23b6e14653c706afc9e8b426777e69310b8f8 /tools/lib/python | |
| parent | 934dcccf3ffc7568fdeb363842bb9fc36e1be608 (diff) | |
clk: renesas: r9a09g057: Add clock and reset entries for TSU
Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2H (R9A09G057) SoC.
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251020143107.13974-2-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions