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authorChen-Yu Tsai <wens@kernel.org>2025-12-21 19:05:08 +0800
committerMark Brown <broonie@kernel.org>2025-12-22 09:00:49 +0000
commite0c8755d44eb85afd40100586076c3dc4b62ee3b (patch)
tree8a290633149c81bc3fce39e88339848011f52efa /tools/perf/scripts/python/bin/stackcollapse-report
parent9448598b22c50c8a5bb77a9103e2d49f134c9578 (diff)
spi: dt-bindings: sun6i: Add compatibles for A523's SPI controllers
The A523 has four SPI controllers. One of them supports MIPI DBI mode in addition to standard SPI. Compared to older generations, this newer controller now has a combined counter for the RX FIFO ad buffer levels. In older generations, the RX buffer level was a separate bitfield in the FIFO status register. In practice this difference is negligible. The buffer is mostly invisible to the implementation. If programmed I/O transfers are limited to the FIFO size, then the contents of the buffer seem to always be flushed over to the FIFO. For DMA, the DRQ trigger levels are only tied to the FIFO levels. In all other aspects, the controller is the same as the one in the R329. Add new compatible strings for the new controllers. Signed-off-by: Chen-Yu Tsai <wens@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20251221110513.1850535-2-wens@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
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