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| author | Inbaraj E <inbaraj.e@samsung.com> | 2025-08-14 19:39:33 +0530 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-08-18 10:46:36 +0200 |
| commit | 1a713bd3b0c60d826bdde633919bedc1fd38df4d (patch) | |
| tree | d28082bd04c5007536dc6ab76d1f51504c6ab5e5 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 5576d8098052952a6c95af86ad3dcb341554ac75 (diff) | |
clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
Add clock id for PCLK and PLL. These clock id will be used for
operation of CSI driver. PCLK is AXI2APB clock used for register
access. PLL clock is main clock source for CAM_CSI block.
Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
Link: https://lore.kernel.org/r/20250814140943.22531-3-inbaraj.e@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions